Generally, shallow trench isolation (hereinafter abbreviated STI) in a semiconductor device plays a role in electrically isolating devices from each other. In STI, a semiconductor substrate is etched in part to form a trench and an insulator fills up the trench to isolate devices from each other. FIGS. 1A to 1F are cross-sectional diagrams depicting a known isolation method in a semiconductor device. Referring to FIG. 1A, a pad oxide layer 2 is formed on a silicon substrate 1, a nitride layer 3 is deposited on the pad oxide layer 2, and a TEOS layer 4 is deposited on the nitride layer 3.
Referring to FIG. 1B, the TEOS, nitride, and pad oxide layers 4, 3, and 2 are etched by photolithography using an ISO mask to expose a surface of the substrate 1 corresponding to a field area. Additionally, the exposed surface of the substrate 1 is etched to form a trench.
Referring to FIG. 1C, an exposed portion of the pad oxide layer 2 is removed by CDE (chemical dry etch) to form an undercut and pull-back is carried out on the exposed nitride layer 3. Subsequently, SAC (sacrificial oxidation is carried out on an inside of the trench to compensate etching damage to the silicon substrate 1 and an oxide layer 5 is then formed on the inside of the trench.
Referring to FIG. 1D, an oxide layer 6 is formed over the substrate including the TEOS layer 4 to fill up the trench and planarization is carried out on the oxide layer 6 by CMP (chemical mechanical polishing) until the TEOS layer 4 is exposed. Subsequently, wet cleaning is carried out on the planarized oxide layer 6 to lower a height of an STI layer 6.
Referring to FIG. 1E, after completion of wet cleaning, a rounded corner having a small radius is formed at an upper corner 8 of the trench and a divot 7 is formed on an upper edge of the STI layer 6.
Referring to FIG. 1F, a gate polysilicon layer 10 is formed on the oxide layer 2 and the STI layer 6 to fill up the divot.
In the known method, CDE is carried out on the pad oxide layer and the pad nitride layer 3 is etched by pull-back to form the undercut beneath the TEOS layer 4, and the trench sidewall corner is rounded by SAC oxidation. However, the known method fails to sufficiently provide the undercut. In case of forming the undercut sufficiently to enlarge the corner rounding, a void occurs in filling up the trench with oxide, and the generated void cracks the TEOS layer on planarizing the filing oxide, whereby device characteristics are degraded. Further, the divot 7 in the vicinity of a boundary of the STI layer 6 brings about RNWE to degrade device characteristics and to lower device throughput.